Abstract
We present a method for the automatic generation of test vectors for functional verification, giving the advantages of random and directed testing. We show the use of a formal specification as input to a test generator. We present techniques for the efficient implementation of the generator. We discuss our experience with this method applied to commercial designs. We show how our approach is a stepping stone towards practical formal verification.
Original language | English |
---|---|
Pages (from-to) | 415-420 |
Number of pages | 6 |
Journal | Proceedings - Design Automation Conference |
Volume | 0 |
Issue number | 0 |
DOIs | |
Publication status | Published - 1996 |
Event | Proceedings of the 1996 33rd Annual Design Automation Conference - Las Vegas, NV, USA Duration: 3 Jun 1996 → 7 Jun 1996 |
ASJC Scopus subject areas
- Hardware and Architecture
- Control and Systems Engineering