TY - JOUR
T1 - Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints
AU - Kritikakou, Angeliki
AU - Catthoor, Francky
AU - Athanasiou, George S.
AU - Kelefouras, Vasilios
AU - Goutis, Costas
PY - 2013/5
Y1 - 2013/5
N2 - A systematic methodology for near-optimal software/hardware codesign mapping onto an FPGA platform with microprocessor and HW accelerators is proposed. The mapping steps deal with the inter-organization, the foreground memory management, and the datapath mapping. A step is described by parameters and equations combined in a scalable template. Mapping decisions are propagated as design constraints to prune suboptimal options in next steps. Several performance-area Pareto points are produced by instantiating the parameters. To evaluate our methodology we map a real-time bio-imaging application and loop-dominated benchmarks.
AB - A systematic methodology for near-optimal software/hardware codesign mapping onto an FPGA platform with microprocessor and HW accelerators is proposed. The mapping steps deal with the inter-organization, the foreground memory management, and the datapath mapping. A step is described by parameters and equations combined in a scalable template. Mapping decisions are propagated as design constraints to prune suboptimal options in next steps. Several performance-area Pareto points are produced by instantiating the parameters. To evaluate our methodology we map a real-time bio-imaging application and loop-dominated benchmarks.
U2 - 10.1145/2459316.2459317
DO - 10.1145/2459316.2459317
M3 - Article
SN - 1544-3566
VL - 10
SP - 1
EP - 25
JO - ACM Transactions on Architecture and Code Optimization
JF - ACM Transactions on Architecture and Code Optimization
IS - 2
ER -