@inproceedings{4a71260e39074d53b5109bd5333f49fa,
title = "Design for reliability for wafer level system in package",
abstract = "This paper discusses the Design for Reliability modellmg of several System-in-Package (SiP) structures developed by NXP and advanced on the basis of Wafer Level Packaging (WLP). Two different types of Wafer Level SiP (WLSiP) are presented and discussed. The main focus is on the modelling approach that has been adopted to investigate and analyse the board level reliability of the presented SiP configurations. Thermomechanical non-linear Finite Element Analysis (FEA) is used to analyse the effect of various package design parameters on the reliability of the structures and to identify design trends towards package optimisation. FEA is used also to gain knowledge on moulded wafer shrinkage and related issues during the wafer level fabrication. The paper provides a brief outline and demonstration of a design methodology for reliability driven design optimisation of SiP. The study emphasises the advantages of applying the methodology to address complex design problems where several requirements may exist and uncertainties and interactions between parameters in the design are common.",
author = "Stoyan Stoyanov and Nadia Strusevich and Jahir Rizvi and Vincent Georgee and Yannou, {Jean Marc} and Chris Bailey",
year = "2008",
doi = "10.1109/ESTC.2008.4684364",
language = "English",
isbn = "9781424428144",
series = "Proceedings - 2008 2nd Electronics Systemintegration Technology Conference, ESTC",
pages = "293--298",
booktitle = "Proceedings - 2008 2nd Electronics Systemintegration Technology Conference, ESTC",
note = "2008 2nd Electronics Systemintegration Technology Conference, ESTC ; Conference date: 01-09-2008 Through 04-09-2008",
}