I am a Lecturer (assistant professor) in Computer Science at the University of Plymouth. My research develops methods that make AI run faster and with lower energy and memory use across diverse platforms, from edge devices to supercomputers. I work on compiler and runtime optimisation for HPC and high-performance embedded systems (CPUs/GPUs/NPUs/FPGAs), efficient DNN inference (compression via low-rank factorisation and pruning, memory-aware execution, adaptive networks), and performance optimisation of tensor/matrix computations for HPC and edge AI. 

I have published over 60 papers, including top-tier journal and conference publications. I have previously served as PI on two small research grants and have contributed to numerous European and international funded projects as a researcher and external collaborator.

I welcome PhD applicants and industry collaborations in AI compilers, performance engineering, DNN compression, and efficient DNN training and inference on heterogeneous systems.

Research Interests:

• AI compilers & performance engineering - hardware-aware optimisation across CPUs, GPUs, NPUs and FPGAs

• Efficient DNN inference (model compression; memory & energy optimisation)

• Adaptive networks (dynamic/conditional computation; compute–accuracy trade-offs)

• Tensor/matrix computation optimisation

• Runtime/task scheduling and memory management for HPC/edge systems

Research Highlights:

• ACM TECS 2025: Optimising Tensor Train decomposition for DNNs on RISC-V using design-space exploration and compiler optimisations, targeting efficient edge deployment.

• ACM TECS 2025: Register blocking via a source-to-source, analytical modelling methodology for affine loop kernels, enabling predictable performance/portable optimisation.

• DATE 2024: A CNN compression methodology for layer-wise rank selection that explicitly accounts for inter-layer interactions, improving compression decisions beyond per-layer heuristics.

• IEEE TPDS 2023: Analytical CPU convolution methodology achieving 1.1×–7.2× speedups vs oneDNN on ResNet-50/DenseNet-121/SqueezeNet layers (112 layers; two platforms).

• IEEE TPDS 2022: CPU 2D convolution methodology achieving 2.8×–40× speedups vs Intel IPP/OpenCV on key image-processing kernels across multiple image sizes and platforms.

Awards:

• HiPEAC Technology Transfer Award (2022) - technology transferred to Think Silicon.

• Best Paper Award, SAMOS XXII - “A Design Space Exploration Methodology for Enabling Tensor Train Decomposition in Edge Devices”.

Editorial roles:

• Editor, Frontiers in High Performance Computing (2024–present).

• Guest Editor in AI-Enhanced Sensing Technologies for Smart Energy Informatics and Sustainable Systems, MDPI (2026).

Program Committee Member:

• 2025–present: AMD Open Hardware Competition - Reviewer / Panel Member

• 2026: ACM International Conference on Supercomputing (ICS) -Program Committee Member

• 2021–2024: ACM Computing Frontiers (CF) Conference - Program Committee Member

• 2018–2023: IEEE International Symposium on Innovation in Information and Communication Technology (ISIICT) - Program Committee Member

1.  “Improving the performance of HiRep Lattice Simulations software by exploiting the CPU/GPU hardware architecture details and algorithm characteristics”, Main Supervisor (DoS) for Dr. Shidur Rahman (2020-2024)
2.  "Optimising Flow Routing Using Network Performance Analysis", 2nd Supervisor for Dr Muna Al-Saadi (2020-2023) 

• Parallel Computing (COMP3001)
• Computer Systems (COMP1001)
• Computing Practice (COMP1004)

• Applicant Day Lead for six CS Programs (2023-present) 
• Admissions Tutor for six CS Programs (2023-present)
• Academic Liaison Person for seven Computing Partner Colleges (2019-present)
• Coordinator of International Partnerships agreements for computing (2023-present)
• HPC Champion (Computing) and HPC Steering Committee member, (2022–present).
• EDI Committee Member (2022-23)